1. Technical Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to semiconductor devices such as standard cells that include logic circuit sections that are designed using a variety of cells according to the customers"" specifications. Furthermore, the present invention also relates to a method for designing such semiconductor devices and a design program.
2. Conventional Technology
Generally, in a semiconductor device, wiring patterns that are connected to transistors or the like formed within a semiconductor substrate are formed with metal wiring layers disposed in several layers over the semiconductor substrate through interlayer dielectric layers. To connect wiring patterns formed in the metal wiring layers to gate electrodes and impurity diffusion layers, or to connect wiring patterns formed in multiple layers to one another, openings (also called xe2x80x9cthrough holesxe2x80x9d or xe2x80x9cvia holesxe2x80x9d) are provided in the interlayer dielectric layers. Metal in an upper layer is filled in the opening of the interlayer dielectric layer to connect the upper layer to gate electrodes, impurity diffusion regions or metal wirings in a lower layer. The metal that fills the openings in the interlayer dielectric layer is called an input/output pin or a relay pin. Adjacent openings cannot be disposed too close to each other, and the pitch of the openings needs to be greater than the minimum pitch that is specified by the design rule.
Also, when a semiconductor device uses standard cells, the semiconductor device is designed while several kinds of cells that specify locations of transistors and wiring patterns included in predetermined circuit blocks are assembled on wring grids. In this case, it may be easy to check the pitch of openings in each cell in advance. However, when cells are combined, it is difficult to check the pitch of openings without actually designing a layout, because many different combinations of such cells are possible.
Dispositions of openings in a semiconductor device will be described with reference to FIG. 5. In FIG. 5, grids shown by solid lines indicate wiring grids, and regions surrounded by broken lines indicate two adjacent cells disposed next to each other in an X direction.
In FIG. 5(a), an appropriate opening pitch that is specified by the design rule is set as a grid interval Dx in the X direction, and therefore an opening 51 and an opening 52 can be disposed next to each other in the X direction.
In FIG. 5(b), a grid interval Dx in the X direction is set to be narrower than the appropriate opening pitch that is specified by the design rule. However, since the opening 51 and the opening 52 are disposed shifted from each other in a Y direction, they still meet the conditions for an appropriate opening pitch.
In FIG. 5(c), a grid interval Dx in the X direction is set to be narrower than the appropriate opening pitch that is specified by the design rule. Also, since the opening 51 and the opening 52 are disposed adjacent to each other in the X direction, they cannot meet the conditions for an appropriate opening pitch.
For this reason, conventionally, grid intervals are set wider, or openings are not disposed in wiring grids adjacent to cell peripheral sections so as not to violate the design rule even when two cell openings are disposed adjacent to each other.
However, there have been demands for higher integration of semiconductor devices in recent years, and higher integration of semiconductor devices cannot be achieved by the conventional design algorithms such as the one described above.
In view of the problems described above, it is an object of the present invention to improve the wiring density by setting narrow grid intervals while satisfying the conditions for appropriate opening pitches specified by the design rule.
To solve the problems described above, a semiconductor device in accordance with the present invention has a layout designed by disposing a plurality of cells including a specified circuit block. The semiconductor device is equipped with: a semiconductor substrate; a plurality of transistors formed in the semiconductor substrate; a first wiring pattern and a second wiring pattern formed respectively in a first cell and a second cell adjacent to each other in a first direction in a wiring layer disposed over the semiconductor substrate, the first wiring pattern and the second wiring pattern having portions extending in parallel with each other in a second direction perpendicular to the first direction; and an interlayer dielectric layer formed as a lower layer of the wiring layer, the interlayer dielectric layer having openings formed at locations corresponding to a first position of the first wiring pattern and a second position of the second wiring pattern that is shifted from the first position in the first direction and the second direction.
Also, a method for designing a semiconductor device includes designing a layout by disposing a plurality of cells including a specified circuit block. The method includes: a step of disposing a plurality of transistors on wiring grids; a step of disposing a first wiring pattern and a second wiring pattern respectively in a first cell and a second cell adjacent to each other in a first direction of the wiring grids in a wiring layer disposed through an interlayer dielectric layer, and a step of disposing the first wiring pattern and the second wiring pattern to have portions extending in parallel with each other in a second direction of the wiring grids perpendicular to the first direction; and a step of forming openings in the interlayer dielectric layer at locations corresponding to a first position of the first wiring pattern and a second position of the second wiring pattern that is shifted from the first position in the first direction and the second direction.
Furthermore, a design program for designing a semiconductor device in accordance with the present invention includes designing a layout by disposing a plurality of cells including a specified circuit block. The design program for the semiconductor device causes a CPU to execute: a process of disposing a plurality of transistors on wiring grids; a process of disposing a first wiring pattern and a second wiring pattern respectively in a first cell and a second cell adjacent to each other in a first direction of the wiring grids in a wiring layer disposed through an interlayer dielectric layer, and a process of disposing the first wiring pattern and the second wiring pattern to have portions extending in parallel with each other in a second direction of the wiring grids perpendicular to the first direction; and a process of forming openings in the interlayer dielectric layer at locations corresponding to a first position of the first wiring pattern and a second position of the second wiring pattern that is shifted from the first position in the first direction and the second direction.
By the present invention thus structured, in the first cell and the second cell disposed adjacent to each other in the first direction, the first wiring pattern and the second wiring pattern are disposed to have portions extending in parallel with each other in the second direction perpendicular to the first direction, and openings in the interlayer dielectric layer are shifted in the second direction. As a result, the wiring density can be improved by setting narrow grid intervals while satisfying the conditions for appropriate opening pitches specified by the design rule.